On a semiconductor substrate that is subjected to a wafer processing, a plurality of semiconductor devices are arranged longitudinally and laterally. These semiconductor devices are divided by dicing and then, incorporated into a semiconductor module.
The above-described semiconductor devices are normally subjected, before being incorporated into the semiconductor module, to an electrical characteristic test for the semiconductor device. For example, FIG. 5 is a configuration view of an apparatus for performing the electrical characteristic test.
FIG. 5 illustrates a state of a static characteristic test for measuring a leakage current between electrodes on vertical semiconductor devices.
A prober (test apparatus) 100 includes a cantilever type probe pin 101, a probe card 102 for supporting the probe pin 101, and a prober stage 104 for supporting a semiconductor substrate 103 as an object to be inspected. Here, as described above, a plurality of vertical semiconductor devices (not illustrated) are arranged in every direction of the semiconductor substrate 103.
On each vertical semiconductor device, a surface structure and a rear surface electrode are formed. On the surface structure, a gate electrode and an emitter electrode are formed. Further, the rear surface electrode serves as a collector electrode, and is configured by a metal film.
When the prober stage 104 is raised, a plurality of probe pins 101 having needlepoints with different diameters contact electrodes on the surface structure, and the vertical semiconductor device with a contacted portion is subjected to the static characteristic test. Further, when a relative position between the probe pin 101 and the semiconductor substrate 103 is changed, the plurality of vertical semiconductor devices are continuously subjected to the static characteristic test on the same stage.
On the other hand, in the electrical characteristic test, a dynamic characteristic test as in a so-called high current switching test is performed in addition to the static characteristic test.
However, in the dynamic characteristic test, a high current of approximately 0 to several hundred amperes is energized within the vertical semiconductor device. Therefore, cracks with a diameter of approximately 100 μm may occur in the defective vertical semiconductor device. For example, FIG. 6 illustrates a relationship between a voltage and current applied to the vertical semiconductor device.
The horizontal axis of FIG. 6 represents the time, and illustrates the variation per hour of a voltage and current in the case where a short circuit occurs in an IGBT (Insulated Gate Bipolar Transistor) device during a turn-off operation of the high current switching test.
As illustrated in FIG. 6, when the turn-off operation is started, a voltage (VCE) between collector and emitter electrodes instantaneously rises up and a collector current (IC) falls down. However, after the short circuit occurs at the time of occurrence of cracks illustrated in FIG. 6, the voltage (VCE) between the collector and emitter electrodes falls down and the collector current (IC) rises up. In other words, FIG. 6 illustrates a state where when the short circuit occurs, a switching operation of the IGBT device is disabled.
Further, in damage within the vertical semiconductor device, a fissure may grow up in a radial pattern from a crack without staying on a portion in which this crack occurs.
As described above, the dynamic characteristic test is not generally performed in a wafer state due to the fact that fissures grow up in a radial pattern in the dynamic characteristic test of the vertical semiconductor device. The reason is that when the dynamic characteristic test is performed in the wafer state, the fissure may grow up to a nondefective vertical semiconductor device adjacent to a defective vertical semiconductor device and therefore, the nondefective vertical semiconductor device receives the damage.
Accordingly, the fact is that a simple body of a semiconductor chip is subjected to the dynamic characteristic test. As a result, there arises the following problem. That is, in the dynamic characteristic test, after the semiconductor substrate is divided into the semiconductor chips by dicing, the individual semiconductor chips are moved up to a prober using a chip handler and a simple body of the semiconductor chip is subjected to the dynamic characteristic test. Therefore, a continuous test fails to be performed on the same stage and therefore, inspection efficiency is reduced.
There is disclosed a method for continuously subjecting a plurality of semiconductor chips to an electrical characteristic test on the same stage without moving the semiconductor chips up to a test apparatus by a chip handler after dividing the semiconductor substrate by dicing (for example, Japanese Laid-open Patent Publication No. 2003-258067).
However, in the above-described known example, a displacement of the semiconductor chips on a support stage, which occurs after the dicing is merely prevented. Accordingly, when cracks that occur in the above-described dynamic characteristic test grow or propagate in a radial pattern, the known example does not prevent the damage from being further expanded. That is, the above-described problem at the time of performing the dynamic characteristic test of the vertical semiconductor device is not yet solved.